Method for the manufacture of a monolithic, static memory cell

US4300279A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventor

• Armin Wieder · Gauting, DE

Key dates

• Filing date: Jul 16, 1980
• Grant date: Nov 17, 1981
• Expiry date: Jul 16, 2000

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/35
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Production of high bit density memory cells using six selective, vertically aligned, reactive plasma etching steps. A gate oxide layer is applied to the boundary surface of the semiconductor layer and has a polysilicon layer which is highly doped and covered with a first intermediate oxide layer. A drive line and the gate are first formed. Sections of the drive line at the ends thereof are removed by isotropic etching and the resulting recesses are filled in a thermal oxidation step. The portion of the gate oxide layer adjacent the structured parts is removed by a second etching step. A second polysilicon layer is deposited, highly doped and covered with a second intermediate oxide layer. Another drive line having a part contacting a doped region in the semiconductor layer, the region being formed by ion implantation, is structured by a third etching step. A recess is then formed by a fourth etching step and an isotropic etching step is performed to remove those parts of the drive line which extend to the last-mentioned recess. A fifth etching step is performed for removing the oxide layer covering the boundary surface of the semiconductor layer within the recess. A third, silicon …