Patent · US Expired

TTL-Compatible address latch with field effect transistors

US4301381A · kind A · utility

5Cited by

5References

6Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Rainer Clemen · Böblingen, DE
Joerg Gschwendtner · Eßlingen, DE
Werner Haug · Thalwil, CH

Key dates

Filing date	Aug 14, 1979
Grant date	Nov 17, 1981
Priority date	—
Expiry date	Aug 14, 1999

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/01855
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.