Packaging process for semiconductors
US4305897A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 18, 1979 |
| Grant date | Dec 15, 1981 |
| Priority date | — |
| Expiry date | Dec 18, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/181
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process for packaging semiconductors or integrated circuits including semiconductors involves positioning a lead frame on which semiconductors or an integrated circuit are mounted between two thermoplastic resin moldings, at least one of which moldings has a cavity for holding the semiconductors or the integrated circuit and thereafter integrally joining the thermoplastic resin moldings under heat and pressure to the lead frame. An uneven surface is provided on at least a part of the surfaces to be joined of either or both of the two thermoplastic resin moldings. This uneven surface is formed around the cavity in a thermoplastic resin molding having a cavity or on a surface of the thermoplastic resin molding having no cavity which corresponds to the surface to be joined to the other thermoplastic molding having a cavity. The lead frame is interposed or arranged between the two thermoplastic resin moldings so that at least one void is formed between the uneven surface to be joined of at least one of the two thermoplastic resin moldings and the lead frame. The thermoplastic resin moldings are joined by the application of heat and pressure to the lead frame so that at least a part o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.