R-S Flip-flop circuit having a predetermined initial operating condition
US4306162A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 29, 1979 |
| Grant date | Dec 15, 1981 |
| Priority date | — |
| Expiry date | Oct 29, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/2865
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The collector-emitter electrodes of each of two NPN transistors having the collector electrode of each direct current cross connected to the base electrode of the other are connected, respectively, across an operating potential source through a collector load resistor element and an active collector load element. A biasing circuit arrangement is effective upon each application of supply potential to activate the active collector load element a period of time later than that at which base-emitter drive current is initiated through the base-emitter junction of the NPN transistor having the collector-emitter electrodes thereof connected across the supply potential source through the active collector load element whereby this transistor is always triggered conductive first upon each application of supply potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.