Data processing apparatus
US4306285A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1979 |
| Grant date | Dec 15, 1981 |
| Priority date | — |
| Expiry date | Jan 4, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30163
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing apparatus including an instruction register and an instruction decoder connected therewith, when a designation instruction (operand changing instruction) is set in the instruction register, the operand (the code of source or destination) of the designation instruction is registered in a source address register or a designation address register connected to the instruction register through a gate circuit. The registers produce control signals through decoders respectively for selecting predetermined operands. When the designation instruction is decoded by the instruction decoder a first (for source) and a second (for destination) flip-flop circuits which are connected to the output terminal of the instruction decoder are set. The outputs of these flip-flop circuits are applied to the negative input of an AND gate circuit connected to the instruction decoder. When an instruction to be executed subsequent to the designation instruction is decoded by the instruction decoder, the instruction decoder produces a control signal that selects the operand of the instruction, but this control signal is selectively blocked by the AND gate circuit, with the result that the o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.