Logic simulation machine
US4306286A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1979 |
| Grant date | Dec 15, 1981 |
| Priority date | — |
| Expiry date | Jun 29, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware logic simulation machine comprised of an array of specially designed parallel processors, with there being no theoretical limit to the number of processors which may be assembled into the array. Each processor executes a logic simulation function wherein the logic subnetwork simulated by each processor is implicitly described by a program loaded into each processor instruction memory. Logic values simulated by one processor are communicated to other processors by a switching mechanism controlled by a controller. If the array consists of i processor addresses, the switch is a full i-by-i way switch. Each processor is operated in parallel, and the major component of each processor is a first set of two memory banks for storing the simulated logic values associated with the output of each logic block. A second set of two memory banks are included in each processor for storing logic simulations from other processors to be combined with the logic simulation stored in the first set of memory banks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.