CMOS P-Well selective implant method
US4306916A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1979 |
| Grant date | Dec 22, 1981 |
| Priority date | — |
| Expiry date | Sep 20, 1999 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/965
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a complementary metal-oxide-silicon (CMOS) integrated circuit device by forming a composite layer of oxide and nitride on the surface of a silicon substrate defined into predetermined areas for the subsequent formation of transistors, masking the substrate to expose preselected areas for P-wells, ion implanting P-type material in the exposed areas to form P-wells so that a relatively high doping level is provided to a greater depth around composite areas within the P-wells areas and a relatively lower doping level is established under the composite layer areas with the P-wells. The ion implantation of P-type material may be accomplished in either a single stage or a two stage procedure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.