Clock check circuit
US4308472A · kind A · utility
19Cited by
3References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 3, 1979 |
| Grant date | Dec 29, 1981 |
| Priority date | — |
| Expiry date | Dec 3, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/19
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An apparatus adapted to check for the continuous presence of an incoming clock pulse train comprising an exclusive OR gate, to the input of which are coupled the clock pulse train and a second train of clock pulses delayed by one half the period of the incoming clock pulse train. A third train of clock pulses delayed by three quarters of the clock period is utilized to strobe the OR gate output into a pair of flip-flops. If the two inputs to the OR gate are the same a fault exists and a flip-flop is set to indicate on which excursion the fault occurred.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.