MOS Memory cell
US4308594A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 31, 1980 |
| Grant date | Dec 29, 1981 |
| Priority date | — |
| Expiry date | Jan 31, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An integrated circuit memory cell (10) having a bit line (12), a word line (14) and a cell voltage supply (26) is provided. The integrated circuit memory cell (10) includes a first clock line (34) and a second clock line (36). A first transistor (20) is interconnected to the bit line (12) and the word line (14) for providing access to the memory cell (10). A second transistor (22) is interconnected to the cell voltage supply source (26) and to the first transistor (20) thereby defining a first node (S). The second transistor (22) provides a charging path from the cell voltage supply source (26) to the first node (S). A capacitor (30) is provided and interconnects the first clock line (34) and the second transistor (22). The interconnection between the capacitor (30) and the second transistor (22) defines a second node (K). The capacitor (30) provides a coupling path between the first clock line (34) and the second node (K) for conditionally supplying a voltage from the first clock line (34) to the second node (K) to render voltage at the second node (K) higher than the cell voltage supply source (26). A third transistor is provided for the memory cell (10) and is interconnected to …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.