Transistor logic tristate device with reduced output capacitance
US4311927A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 18, 1979 |
| Grant date | Jan 19, 1982 |
| Priority date | — |
| Expiry date | Jul 18, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0826
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A transistor logic tristate output gate or device is provided with active or passive element arrangements coupled between the enable gate on the one hand and the base of the pull down element transistor on the other hand. This coupling affords a low impedance route to ground or low potential from the base of the pull down element when the enable gate is at low potential and the output device is in the high impedance third state. Miller feedback current at the base of the pull down element transistor is thereby diverted to ground. The coupling arrangement affords high impedance to current flow in the opposite direction thereby blocking current flow from the enable gate when the enable gate is at high potential. For active discharge of Miller current three transistors are provided in a double inversion series coupling between the enable gate and pull down element. Alternately a multiple emitter junction transistor is used. For passive element discharge of Miller current a low forward impedance high backward impedance large surface area diode is used.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.