Refresh system for a dynamic memory
US4313180A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 1980 |
| Grant date | Jan 26, 1982 |
| Priority date | — |
| Expiry date | Jan 30, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH02J9/06
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic apparatus comprises a central processor unit (CPU) for controlling the operation of the electronic apparatus, and a dynamic random access memory (RAM). The CPU develops a refresh control signal for refreshing the memory data stored in the dynamic RAM. An additional refresh control circuit is provided outside of the CPU for developing another refresh control signal. The additional refresh control circuit is connected to receive the electric power from a backup battery included in the electronic apparatus. When the service interruption occurs, the additional refresh control circuit is enabled to maintain the memory data stored in the dynamic RAM.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.