Method of fabricating improved radiation hardened self-aligned CMOS having Si doped Al field gate
US4313768A · kind A · utility
20Cited by
11References
10Claims
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Key dates
| Filing date | Apr 6, 1978 |
| Grant date | Feb 2, 1982 |
| Priority date | — |
| Expiry date | Apr 6, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/038
Abstract
A radiation hardened CMOS formed by applying a radiation hard gate oxide layer on a silicon substrate, by applying silicon doped aluminum gates on the gate oxide, and by ion implanting and annealing source and drain regions using said gates as masks at a temperature of or below 500 degrees centigrade. Using an N.sup.- type substrate, a P.sup.+ guard ring is formed at the interface of the P.sup.- well of the N channel MOS device and the N.sup.- substrate before the formation of the gate oxide.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.