Processing element for parallel array processors
US4314349A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 31, 1979 |
| Grant date | Feb 2, 1982 |
| Priority date | — |
| Expiry date | Dec 31, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/006
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processing element constituting the basic building block of a massively-parallel processor. Fundamentally, the processing element includes an arithmetic sub-unit comprising registers for operands, a sum-bit register, a carry-bit register, a shift register of selectively variable length, and a full adder. A logic network is included with each processing element for performing the basic Boolean logic functions between two bits of data. There is also included a multiplexer for intercommunicating with neighboring processing elements and a register for receiving data from and transferring data to neighboring processing elements. Each such processing element includes its own random access memory which communicates with the arithmetic sub-unit and the logic network of the processing element.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.