Interface between a microprocessor chip and peripheral subsystems
US4315308A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 21, 1978 |
| Grant date | Feb 9, 1982 |
| Priority date | — |
| Expiry date | Dec 21, 1998 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An interface between a microprocessor chip and input/output, and memory modules. The interface uses a single, bidirectional bus comprised of a number of lines which is less than the number necessary to carry a complete address word or a full width data word. Information transfer is effected by transferring information in small portions utilizing two or more interface clock cycles. An encoded control specification placed on the bus during the first cycle of information transfer specifies the type of access, the direction of transfer, and the length (number of bytes) of data to be moved. Only two additional simplex lines, one from the microprocessor and the other to the microprocessor are needed to complete the basic interface.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.