Servo loop processor
US4316193A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 1, 1979 |
| Grant date | Feb 16, 1982 |
| Priority date | — |
| Expiry date | Oct 1, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01S11/02
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A servo loop processor suitable for use in a passive radar range determining system is disclosed. Early and late overlapping video pulse trains derived from spaced receiving antennas are fed to separate first and second channels and are sampled and held from pulse period to pulse period to form signals representing the amplitude envelopes of the received pulse trains. The output of the first channel is variably delayed and the delayed signal is compared with the undelayed output of the second channel to create an error signal. The output of the second channel is also differentiated, and the result is sampled and held to create a reference signal that has the proper phase relationship with the error signal so that the error signal can be multiplied by the reference signal to create a correction signal. The resulting correction signal is integrated and fed back to control the time delay applied to the output of the first channel such that a closed servo loop is formed. At balance, the integrated correction signal is related to the distance between the radar antenna transmitting the pulse trains, and the receiving antennas. In an alternative embodiment, envelope signals representing t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.