High speed synchronization circuit
US4317053A · kind A · utility
11Cited by
4References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 5, 1979 |
| Grant date | Feb 23, 1982 |
| Priority date | — |
| Expiry date | Dec 5, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In a high speed synchronizing circuit, the rising edge of an asynchronous input signal is used to set an input RS flip-flop. First and second latch registers monitor the input RS flip-flop. Each latch register generates a reset signal before a change in the logic level of the system clock for resetting the input RS flip-flop. The reset pulses are very narrow which enables the RS flip-flop to be quickly conditioned to receive the next asynchronous signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.