MOS Integrated circuit
US4318117A · kind A · utility
4Cited by
0References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1979 |
| Grant date | Mar 2, 1982 |
| Priority date | — |
| Expiry date | Nov 13, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
A MOS integrated circuit including P-channel MOS transistors, particularly for C-MOS inverter, in which the P-channel MOS transistor (12) has P.sup.+ drain (34), P.sup.+ source (36) connected to a +VDD circuit (42) via P.sup.+ and N.sup.+ diffusion layers (36.sub.1, 36.sub.2) and isolation gate (38). The P.sup.+ layer is partly replaced by, i.e. parallel- and/or serial-connected to the N.sup.+ layer so that an effective source diffusion resistance (R.sub.S) or the conductive resistance (R.sub.0) is lowered.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.