Retro-etch process for integrated circuits
US4318759A · kind A · utility
10Cited by
7References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 21, 1980 |
| Grant date | Mar 9, 1982 |
| Priority date | — |
| Expiry date | Jul 21, 2000 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of electrically isolating a plurality of semiconductor integrated circuit components and for forming gate elements for silicon gate transistors is disclosed whereby extremely narrow line widths can be formed which heretofore have been unattainable by practicing conventional photolithography.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.