Method and circuit arrangement for discharging bit line capacitances of an integrated semiconductor memory
US4319344A · kind A · utility
4Cited by
7References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 30, 1980 |
| Grant date | Mar 9, 1982 |
| Priority date | — |
| Expiry date | May 30, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/416
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and arrangement is provided for selecting and discharging a pair of bit lines of a plurality of charged pairs of bit lines of a memory circuit having cells of the merged transistor logic type. A selected pair of bit lines is discharged through a selected cell coupled to the selected pair of bit lines while simultaneously the remaining or non-selected pairs of bit lines are discharged through a common switch into non-selected word lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.