Self-correcting memory system
US4319356A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 1979 |
| Grant date | Mar 9, 1982 |
| Priority date | — |
| Expiry date | Dec 19, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-correcting memory system includes internal error detection and correction circuitry that periodically accesses each data word and a group of ECC check bits associated with each data word stored in the memory system. The error detection and correction circuitry includes an ECC checking circuit that receives the accessed data word, generates ECC bits, and compares those ECC bits to the group of ECC check bits associated with the data word. The resulting signal is used to correct any single bit in error, and to indicate the presence of a double bit error. A self-correct address counter is cascaded to a refresh address counter in the control circuitry of the memory system so that the accessing of each data word occurs during a refresh cycle of the memory system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.