Method of making self-aligned device
US4319395A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1979 |
| Grant date | Mar 16, 1982 |
| Priority date | — |
| Expiry date | Jun 28, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/0212
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A self-aligned MOS transistor having improved operating characteristics and higher packing density and a method for fabricating the device. Resistance of the gate electrode is reduced substantially by forming the electrode of a metal silicide. Resistance of the source and drain regions is likewise reduced substantially by forming a metal silicide in the doped junction region which allows those regions to be smaller and to require less area. The silicided source and drain regions are self-aligned with and closely spaced to the silicided gate electrode. This is provided by a process which utilizes and makes possible an undercut etching of a polycrystalline silicon gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.