Smaller memory cells and logic circuits
US4320312A · kind A · utility
5Cited by
8References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 2, 1978 |
| Grant date | Mar 16, 1982 |
| Priority date | — |
| Expiry date | Oct 2, 1998 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A method and device are disclosed for reducing the circuit size of a class of circuits including many memory cells and logic circuits. Selected drain to bulk or source to bulk transistor junctions are made leaky. The leaky junctions perform their intended (non-leaky) functions as well as the functions of certain other circuit elements. These other elements may therefore be eliminated from the circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.