Fail-safe and gate circuit
US4320315A · kind A · utility
1Cited by
4References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 20, 1979 |
| Grant date | Mar 16, 1982 |
| Priority date | — |
| Expiry date | Apr 20, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/007
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A fail-safe AND logic circuit including a free-running multivibrator and a pair of voltage reference networks. The multivibrator includes a pair of common emitter transistor amplifiers. The transistor amplifiers are separately biased and powered by an individual one of a pair of voltage reference networks so that a.c. oscillations are produced by the multivibrator when a separate negative-going pulse coincidentally appears on both of the pairs of voltage reference networks.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.