Hybrid bit clock servo
US4320420A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 3, 1980 |
| Grant date | Mar 16, 1982 |
| Priority date | — |
| Expiry date | Jul 3, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N2201/04794
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit for controlling the clock rate separately for each facet of a polygon used in a laser driven raster output scanner. The clock rate for facet #0 is servoed using a first order integrator (11) driven by a digital correction circuit which compares the actual number of pulses against the required number, and produces therefrom an analog correction pulse width which is applied to the integrator (11). A second order integrator (19) is used to compensate for leakage of charge from the parallel capacitor of the first order integrator (11), to improve performance. The remaining facets are then corrected for by assigning to each an individual correction voltage. This correction voltage is generated by counting clock pulses for each additional facet and using these pulse totals to generate individual analog correction voltages which are added to, or subtracted from the facet #0 voltage in an adder (18) which combines the facet #0 correction voltage with each individual voltage in sequence. The result is a relatively simple and inexpensive circuit that compensates for facet signature errors, as well as errors produced by drive motor hunting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.