LSI Circuit logic structure including data compression circuitry
US4320509A · kind A · utility
55Cited by
6References
10Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 19, 1979 |
| Grant date | Mar 16, 1982 |
| Priority date | — |
| Expiry date | Oct 19, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/27
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A logic structure for an LSI digital circuit includes data compression circuitry for deriving a signature word from the data on a multiplicity of internal nodes which are not directly accessible from the terminals of the circuit. The signature word provides error information concerning the data on the internal nodes which are not otherwise available for testing purposes. The addition of data compression circuitry facilitates the testing of LSI digital circuits and can be complemented with minimal overhead chip area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.