Data processing system having centralized data alignment for I/O controllers
US4321665A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 1979 |
| Grant date | Mar 23, 1982 |
| Priority date | — |
| Expiry date | Jan 31, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4013
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system which includes a central processing unit (CPU), main memory and a plurality of input/output controllers (IOCs) connected to a common bus information can be transferred between the main memory and CPU and main memory and the IOCs. Logic is provided within the CPU to align a byte of data on the data lines of the common bus such that it can be taken from the data lines by the main memory and written into a multi byte word without further alignment. Logic is provided within the CPU to extract from a multi byte word of data read from main memory and appearing on the common bus data lines the appropriate byte of data and to align it on the common bus data lines such that an IOC may pass the data byte to a peripheral device without further alignment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.