Circuit for reducing the limit cycle in a digital filter
US4321685A · kind A · utility
Inventors
Key dates
| Filing date | Nov 19, 1979 |
| Grant date | Mar 23, 1982 |
| Priority date | — |
| Expiry date | Nov 19, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03H17/0461
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit arrangement of a digital filter comprises an A/D converter supplied with an input analog signal and producing as output a pulse-modulated digital signal, a digital filter for subjecting the digital signal from the A/D converter to a digital operation processing of finite word length, a D/A converter supplied with the resulting output digital signal of the digital filter and converting the same into an analog signal thereby to generate an output analog signal, an input detector for detecting the state wherein there is substantially no input analog signal and responsively producing as output a detection signal, an integrator for integrating the output of the D/A converter, a switching circuit for operating in response to the output detection signal of the input detector to pass the resulting output signal of the integrator, a reference voltage source, and an adder for adding the signal thus passed by the switching circuit and a reference voltage from the reference voltage source and feeding back and imparting the sum signal thus obtained to the A/D converter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.