Method of electron beam exposure
US4322626A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 25, 1980 |
| Grant date | Mar 30, 1982 |
| Priority date | — |
| Expiry date | Jun 25, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/30
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of electron beam exposure for directly writing patterns on chips of a semiconductor wafer with an electron beam, in which each of the chips is sectioned into a plurality of exposure fields, and at least one alignment mark is formed in only one exposure field of eachg chip. The alignment of the entire wafer with the electron beam is preliminarily adjusted, the alignment of a particular chip with the electron beam is adjusted relying on the alignment mark on the chips, and the exposure fields of the desired chip are successively exposed to the electron beam so that the entire chip is exposed. The remaining chips are successively adjusted in alignment and exposed in the same manner as defined above, whereby the entire wafer is exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.