Instruction fetch circuitry for computers
US4325118A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 3, 1980 |
| Grant date | Apr 13, 1982 |
| Priority date | — |
| Expiry date | Mar 3, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1678
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention is used in a computer system to buffer the transfer of program portions from a system having a first bus width to instruction processing logic having a second bus width. An instruction register receives program portions via a system bus from the program memory. A state register stores a code specifying the action to be taken to transfer the next program portion from the instruction register to the instruction processing logic. Control logic, upon receiving a request for the next program portion from the instruction processing logic, inspects the state register to determine whether the next program portion in sequence should be retrieved from the memory and stored in the instruction register. In addition, the control logic transfers the appropriate program portion to the instruction processing logic, and updates the state register code in preparation for the next request from the instruction processing logic.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.