Circuit for combining delta modulated signals
US4325139A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 28, 1980 |
| Grant date | Apr 13, 1982 |
| Priority date | — |
| Expiry date | Aug 28, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04M3/561
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A circuit for combining a plurality of delta modulated speech signals, each signal being represented by a stream of input bits. Once each clock cycle, a multiplexer (101) sequentially applies one bit from each of the streams to an up-down counter (103) to either increment or decrement a count contained therein. The state of the most significant bit position of the up-down counter is then stored in a D-type flip-flop (104). A feedback bit assumes the inverse state of the stored most significant bit position and is sequentially applied under the control of a binary counter (102) to the up-down counter along with a bit from each of the streams during the next clock cycle. An output bit assumes the state of the stored most significant bit position, and an output signal consisting of a plurality of output bits from successive clock cycles represents the approximate linear sum of the delta modulated speech signals. The application of the feedback bit to the up-down counter can be controlled by the binary counter so that the output signal can represent either a reduced or an amplified linear sum of the delta modulated speech signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.