Circuit for monitoring the voltage stress of a capacitor

US4326230A · kind A · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Michael Becker · Knittlingen, DE
• Klaus Renz · Fürth, DE
• Manfred Weibelzahl · Fairview Avenue, DE
• Alfons Fendt · Erlangen, DE
• Dusan Povh · Nuremberg, DE
• Gerhard Schuch · Erlangen, DE
• Hermann Waldmann · Radebeul, DE

Key dates

• Filing date: Jul 3, 1980
• Grant date: Apr 20, 1982
• Expiry date: Jul 3, 2000

Classification

• Technology area (CPC H): Electricity
• CPC primary: H02H7/16
• WIPO field: Electrical machinery, apparatus, energy
• WIPO sector: Electrical engineering

Abstract

A circuit for monitoring the voltage stress of a capacitor which produces an over-stress indicator signal responsive to the over-voltage history of the capacitor. If the measured voltage stress of the capacitor exceeds a predetermined over-voltage value, a characteristic-curve generator, having a predetermined transfer function, produces an output signal which is responsive to the measured voltage stress of the capacitor and the transfer function of the characteristic-curve generator. This signal is combined with a further signal which is responsive to a predetermined permissible continuous operation voltage value. The combined signals are conducted to an integrator having a predetermined integration time constant for producing an overload signal. The overload signal at the output of the integrator is a measure of the state of stress of the capacitor. Circuitry may be provided for disconnecting the capacitor from a transmission line in response to the output signal of the integrator. Also, plural capacitor voltage stress monitoring stages may be combined to monitor the capacitor voltage stress in a plurality of over-voltage ranges.