CMOS Transistor pair with reverse biased substrate to prevent latch-up
US4327368A · kind A · utility
28Cited by
3References
7Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 19, 1979 |
| Grant date | Apr 27, 1982 |
| Priority date | — |
| Expiry date | Sep 19, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/854
Abstract
A complementary type MOS transistor device is disclosed including a p-channel type MOS transistor having source, drain and gate regions formed in the n-well region which is formed in the surface area of a p-type semiconductor layer and an n-channel MOS transistor having source, drain and gate regions formed in said semiconductor layer. The semiconductor layer is formed on an n-type semiconductor body and a reverse bias voltage is applied between the semiconductor layer and the semiconductor substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.