Dynamic memory refresh system with additional refresh cycles
US4328566A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 24, 1980 |
| Grant date | May 4, 1982 |
| Priority date | — |
| Expiry date | Jun 24, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention is particularly directed to the enabling of a refresh cycle for a dynamic memory chip at a period in the fetch cycle, for example, of a type 8085 microprocessor, when the normal timing of the chip does not permit addressing of the memory. Specifically, in the fetch cycle, a fourth clock period occurs following a memory read pulse. This fourth clock cycle is required for the application of the microprocessor, but does not involve any addressing of the memory. Accordingly, in accordance with the invention, upon the occurrence of a memory read cycle, during which a normal refresh occurs, the refreshing circuitry is reactivated, so that a further refresh cycle will occur during this fourth clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.