Controlled selective disconnect system for wafer scale integrated circuits
US4329685A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 9, 1980 |
| Grant date | May 11, 1982 |
| Priority date | — |
| Expiry date | Jun 9, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/832
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure relates to a controlled selective power disconnect means for employment with the various circuits implemented on a crystalline wafer so that a particular circuit can be selectively disconnected when it has developed a defect or short or is unwanted in the system for other reasons. The disconnect means employs a gate between the power source and the circuit, which gate is controlled by a fuse that can be melted or blown by a power disconnect signal thereby opening the gate. An amorphous switch can also be used such that networks can expand or contract around defective chips as required by the particular task or tasks involved.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.