Demodulator arrangement
US4330863A · kind A · utility
Inventor
Key dates
| Filing date | Mar 7, 1980 |
| Grant date | May 18, 1982 |
| Priority date | — |
| Expiry date | Mar 7, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L27/2275
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A demodulator arrangement having a demodulator and a digital phase locked loop responsive to input diphase digitally modulated signals to produce output signals which are applied to the demodulator for effecting the demodulation of the input signals. The phase locked loop includes a phase comparator in which the timing of transitions in the input signals is compared with the timing of transitions in the output signals obtained from a clock signal by means of a variable divider and a counter arranged to count upwards and downwards selectively the outputs of the phase comparator and adjust the variable division factor in accordance with the total recorded by the counter so as to tend to synchronize the output signal with the input signals. A phase adjustment circuit is provided responsive to the output of the demodulator and the output signals of the digital phase locked loop to correct the phase of the output signals. In the phase adjustment circuit, phase errors are counted and when sufficient have occurred the phase jump is caused by altering a counter in the variable divider.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.