Three layer floating gate memory transistor with erase gate over field oxide region
US4331968A · kind A · utility
61Cited by
6References
2Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 17, 1980 |
| Grant date | May 25, 1982 |
| Priority date | — |
| Expiry date | Mar 17, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A field effect transistor storage device for use in programmable read-only memories of the type employing a floating gate and a control gate overlying and aligned with the floating gate. An erase gate is provided adjacent at least one edge of the floating gate for removing charge stored on the floating gate. A method of electrically erasing the storage device includes holding the control gate at a fixed potential to thereby hold the floating gate at a substantially fixed potential while a relatively low voltage is applied to the erase gate to remove charge stored on the floating gate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.