Microcomputer with branch on bit set/clear instructions
US4334268A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1979 |
| Grant date | Jun 8, 1982 |
| Priority date | — |
| Expiry date | May 1, 1999 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30058
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-chip microcomputer comprises a central processor unit (100), a random access memory (110), a read only memory (120), internal timing circuitry including a timer counter (131), and three I/O data ports (140, 150, and 160). Included within the instruction set of the microcomputer are a branch on bit set instruction and a branch on bit clear instruction. The branch on bit set instruction is a three-byte instruction in which the first byte represents the op code including a designation of a particular bit to be examined, the second byte represents the address of a memory location in which the designated bit is to be examined, and the third byte represents an offset which when combined with the contents of the program counter designates a memory location to which a branch is to be taken if the designated bit is in fact set. For the branch on bit clear instruction, a branch is performed when the particular bit examined is determined not to be set. The branch on bit set and branch on bit clear instructions facilitate serial I/O operations by the microcomputer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.