Retro-etch process for forming gate electrodes of MOS integrated circuits
US4334348A · kind A · utility
8Cited by
8References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 5, 1981 |
| Grant date | Jun 15, 1982 |
| Priority date | — |
| Expiry date | Mar 5, 2001 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/947
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of electrically isolating a plurality of semiconductor integrated circuit components and for forming gate elements for silicon gate transistors is disclosed whereby extremely narrow line widths can be formed which heretofore have been unattainable by practicing conventional photolithography.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.