Digital frequency multiplier
US4339722A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 20, 1980 |
| Grant date | Jul 13, 1982 |
| Priority date | — |
| Expiry date | May 20, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/00006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital frequency multiplier which includes a first counter for counting the number of clock pulses received from a generator having first been divided by N in a divider. The counter establishes the number of these pulses which occur during a cycle of the incoming frequency and this number is compared in a comparator with the count from a further clock counter. Typically when coincidence occurs a change of state of the comparator results and as this coincidence will occur N times during a cycle of the incoming frequency, the output repetition frequency from the comparator will be N times the incoming frequency. Although division can be provided prior to the first counter this can alternatively be provided after this counter by using an arithmetic divider.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.