Series-connected two-terminal semiconductor devices and their fabrication
US4339870A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 13, 1980 |
| Grant date | Jul 20, 1982 |
| Priority date | — |
| Expiry date | Nov 13, 2000 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/977
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of fabricating a series-connected combination of two-terminal semiconductor devices on a common substrate comprising: forming a layer of high quality semiconductor material, 4, on the surface of a temporary substrate, 2 and 3, to provide active areas for the devices, forming first contact pattern conductors, 6, 9, 10, on the free surface of the high quality semiconductor layer to provide a separate first contact to this layer for each of the devices, bonding an insulating support substrate, 12, to the first contact pattern, removing the temporary substrate, forming second contact pattern conductors, 17, 18, 19, on the other surface of the high quality layer to provide a separate second contact to this layer for each of the devices, removing regions, 8, of the high quality layer separating the conductors of a pattern at any stage after beginning formation of the first contact pattern in order to define the device active areas so that parts of the first contact pattern are exposed when both the temporary substrate and the regions of the high quality layer have been removed, and providing interconnections between the exposed parts, 10, of the first contact pattern and parts o…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.