Nonvolatile semiconductor memory circuits
US4342101A · kind A · utility
28Cited by
1References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 31, 1980 |
| Grant date | Jul 27, 1982 |
| Priority date | — |
| Expiry date | Oct 31, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C14/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An NMOS non-volatile latch having N-channel drivers Q.sub.1 and Q.sub.2 and variable threshold N-channel FATMOS transistors Q.sub.3 and Q.sub.4 as depletion loads. The control gate of each FATMOS transistor is coupled to its own node (X.sub.1 or X.sub.2) so as to operate in depletion, whereas to obtain the correct voltage stresses the tunnels of the FATMOS floating gates are cross-coupled to the opposite latch nodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.