Semiconductor memory array
US4342102A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jun 18, 1980 |
| Grant date | Jul 27, 1982 |
| Priority date | — |
| Expiry date | Jun 18, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved read-only memory arrangement for generating a differential output signal within the memory array itself incorporates a column of reference cell transistors and a single reference bit line within the same general area occupied by the memory cell transistors and memory main bit lines. Each word line is coupled to the gate of one of the reference cell transistors as well as to the gates of the memory cell transistors lying in the same row. The reference bit line voltage is maintained substantially midway between the high and low potential levels of the main bit lines to produce a differential output voltage for sensing purposes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.