Combined DMOS and a vertical bipolar transistor device and fabrication method therefor
US4344081A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1980 |
| Grant date | Aug 10, 1982 |
| Priority date | — |
| Expiry date | Apr 14, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/406
Abstract
This disclosure relates to an improved DMOS semiconductor type device which can function both as a DMOS (unipolar) type device and as a bipolar transistor device. The DMOS device has two separated source regions of, for example, N+ conductivity and each of these source regions is surrounded by a P- type region, thus providing a pair of channels between each N+ source region and a common N type drain region located between the P- regions. A gate electrode is disposed over both of the channels and functions to permit electrons from the N+ source regions to flow across the P- channels into the common N type drain region when a proper bias is applied to the gate region. Each of the source regions has its own electrode and a separate electrode is provided to each of the P- regions that surround each of the respective N+ source regions. Thus, the DMOS type structure can function as a DMOS device with the electrodes to the source regions serving as source electrodes and the gate electrode functioning to permit electron flow from the separated source regions to a common drain region. Alternatively, one of the electrodes to the N+ source region could function as an emitter (or a source elec…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.