Balanced modulator
US4344188A · kind A · utility
19Cited by
5References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1980 |
| Grant date | Aug 10, 1982 |
| Priority date | — |
| Expiry date | Oct 9, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03D2200/0043
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A balanced modulator for use at the mixer stage of the front end of a signal receiver. The modulator has a transistor balanced modulation circuit of the double balanced type having a plurality of emitter coupled transistor pairs, a circuit for increasing the bias current in the balanced modulation circuit corresponding to an increase in the input signal level, and a circuit for reducing the local oscillation signal applied to the balanced modulation circuit corresponding to an increase in the input signal level so that distortion in the balanced modulation circuit is reduced over a wide range of the level of the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.