Relating to cached multiprocessor system with pipeline timing
US4345309A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1980 |
| Grant date | Aug 17, 1982 |
| Priority date | — |
| Expiry date | Jan 28, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/084
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cached multiprocessor system operates in an ordered pipeline timing sequence in which the time slot for use of the cache is made long enough to permit only one cache access. Further, the time slot for data transfers to and from the processors succeeds the time slot for accessing the cache. The sequence is optimized for transactions that require only one cache access, e.g., read operations that hit the cache. Transactions that require two cache accesses must complete the second cache access during a later available pipeline sequence. A processor indexed random access memory specifies when any given processor has a write operation outstanding for a location in the cache. This prevents the processor from reading the location before the write operation is completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.