ECC Check bit generation using through checking parity bits
US4345328A · kind A · utility
39Cited by
3References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 30, 1980 |
| Grant date | Aug 17, 1982 |
| Priority date | — |
| Expiry date | Jun 30, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus for and method of providing single bit error correction and double bit error detection using through checking parity bits. A coding scheme is implemented which uses through checking parity bits appended to each byte as check bits. The remaining check bits are generated such that the combination of through checking parity bits and remaining check bits together provide single bit error correction and double bit error detection.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.