Emitter coupled logic circuit with active pull-down
US4347446A · kind A · utility
25Cited by
8References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 10, 1979 |
| Grant date | Aug 31, 1982 |
| Priority date | — |
| Expiry date | Dec 10, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An emitter coupled logic gate incorporating an active pull-down transistor in the pull-down circuit with bias connections for the pull-down transistor including components in the differential input circuit of the gate so that the pull-down transistor is active only during a HIGH-to-LOW transition of the output logic signal. Single and plural input gates are described together with advantageous exemplary embodiments of integrated circuits utilizing active pull-down ECL gates formed on an IC chip to enable large signal fan-out to other circuits formed on the same IC chip or to off-chip utilization circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.