Circuit arrangement for time division multiplex data transmission with a bus system
US4347602A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 1, 1979 |
| Grant date | Aug 31, 1982 |
| Priority date | — |
| Expiry date | May 1, 1999 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/0811
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An arrangement is disclosed for time division multiplex data transmission with a bus system which includes a bus line and a plurality of participators or terminals connected to the bus line in data transmitting connection with each other in a predetermined succession in a predetermined combination, in which each participator or terminal has at least one programmable counter having a counting input for connection with a synchronizing signal generator and an output for connection with a switching device to produce a data transmitting connection between the bus line and a data source or sink of this participator or terminal, whereby the counters of all participators or terminals are synchronized with each other. The arrangement includes apparatus to detect short circuits and to shut down individual sections of the bus line to protect the individual sections without shutting down all sections.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.