Address pairing apparatus for a control store of a data processing system
US4348724A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 15, 1980 |
| Grant date | Sep 7, 1982 |
| Priority date | — |
| Expiry date | Apr 15, 2000 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/265
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processing system includes a first memory for storing microinstructions in a first plurality of storage locations and second memory for storing microinstructions in a second plurality of storage locations. A central processor executing a series of addressed microinstructions to control the functions performed by this system generates the address of the next microinstruction to be executed in series as well as a next address selection signal. Addressing circuitry concurrently applies the next address generated by the processor to address inputs of each of the first memory and the second memory. After a predetermined delay, either the first memory or the second memory is selected to output an address microinstruction responsive to the value of the next address selection signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.