Apparatus for digital demodulation or modulation of television chrominance signals
US4349833A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 8, 1980 |
| Grant date | Sep 14, 1982 |
| Priority date | — |
| Expiry date | Sep 8, 2000 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N11/04
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
If an N.T.S.C. signal is to be demodulated using a line-locked sampling rate such as 800 times the line frequency, the ratio between the sampling period and the subcarrier period has the awkward value of 455/1600. Line-locked sampling is nevertheless desirable, e.g. in digital standards conversion. The subcarrier digital signals for digital demodulation are derived with the correct frequency from the sampling rate clock pulses CP by an adder and accumulator into which the number 582 is added modulo-2048 (the register is an 11-bit register) to generate an 11-bit number which represents the subcarrier phase angle at each sampling pulse and which addresses a ROM providing sin and cos values representing subcarrier samples. 582/2048 is not exactly equal to 455/1600 but 2048 is a desirable denominator as it is a power of 2 and implies a ROM of suitable size. ##EQU1## is exactly equal to 455/1600. Another adder and accumulator counts modulo-40960 by increments of 16384 and when this adder overflows, an extra 1 is added in through the carry-in to the first adder. Modulo 40960 is set up by altering 10256 to 40960 when the overflow occurs. Alternative numerical values are disclosed which ap…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.